Copper interconnect technology is a new semiconductor manufacturing process that the semiconductor integrated circuit interconnects are manufactured by using the copper material instead of the conventional aluminum interconnect material. Since the thickness of interconnect layer can be reduced by using the copper interconnects, therefore the distributed capacitance between the interconnect layers is decreased, which makes it possible to provide high frequency chips. However, with the wafer dimension increasing, the process technology node decreasing and the integration degree increasing, the device's reliability requirements are becoming more stringent, and the existing copper interconnect processes is challenged to meet higher requirements.
FIG. 1 is a flow chart for illustrating a prior art method of forming copper interconnects; as shown in FIG. 1, the prior art method of forming copper interconnects includes:
Step S11: depositing a low k dielectric layer on an upper surface of a silicon wafer substrate.
FIG. 2 is a sectional view of structure of the prior art semi-manufactured product after step S11; as shown in FIG. 2, a low k dielectric layer 102 is deposited on the silicon water substrate 101.
Step S12: forming vias or trenches in the dielectric layer by photolithography and etch processes.
FIG. 3 is a sectional view of structure of the prior art semi-manufactured product after step S12; as shown in FIG. 3, the vias or trenches 103 are formed in the dielectric layer 102 by the photolithography and etch processes, which are used to form copper interconnects in the subsequent processes.
Step S13: depositing a barrier layer and a copper seed layer by a physical vapor deposition process.
FIG. 4 is a sectional view of structure of the prior art semi-manufactured product after step S13; as shown in FIG. 4, the barrier layer 104 and the copper seed layer 105 are formed by the physical vapor deposition process.
Step S14: depositing a copper layer by an Electrochemical Copper Plating (ECP) process on the copper seed layer.
FIG. 5 is a sectional view of structure of the prior art semi-manufactured product after step S14; as shown in FIG. 5, the copper layer (unannealed) 106 is deposited by the process of the Electrochemical Copper Plating on the copper seed layer 105.
Step S15: forming the half-finished copper interconnects by an annealing process.
FIG. 6 is a sectional view of structure of the prior art semi-manufactured product after step S15; as shown in FIG. 6, the half-finished copper interconnects (annealed) 107 is formed by the process of the annealing.
Step S16: polishing the half-finished copper interconnects surface to be flush with the dielectric material surface by performing a chemical mechanical planarization process, so as to form a finished copper interconnects.
FIG. 7 is a sectional view of structure of the prior art semi-manufactured product after step S16; as shown in FIG. 7, the half-finished copper interconnects 107 surface is polished to be flush with the dielectric material layer 102 surface by using chemical mechanical planarization (CMP), so as to form the finished copper interconnects 108.
In the method of forming copper interconnects as shown in the FIG. 1, in the Electrochemical Copper Plating process of step S14, since the pattern densities and critical dimensions are different in each area on the same chip, the thickness of copper layer by the Electrochemical Copper Plating process is different, such as, in the area with small dimension and high density pattern, the thickness of the copper layer would be increase, which is over-plating. In the copper polishing process of the subsequent step S16, the polishing pressures in different areas are different due to the difference in surface topography of the half-finished copper interconnects before polishing; in addition, since the polishing rate of copper is much higher than those of the barrier layer and the dielectric layer by using high selective ratio polishing slurry, the difference in pattern densities on the chip will affect the quality of the polished surface, for example, there are erosions 109 are formed in the regions with large critical dimension or the regions with high pattern density, and the polishing residues 110 are also formed in some regions. Therefore, the occurrence of erosions 109 and the polishing residues 110 reduce the effective thickness of the copper in the copper interconnects and the reliability of devices. The polishing residues 110 includes copper residues, residual copper reactants (copper oxide, etc.) and organic residues. The polishing residues 110 inside of the erosion 109 are tightly adhered to the surface of the erosion 109, which cannot be removed even in the subsequent cleaning processes.
In order to effectively solve the defects of copper surface topography in the conventional copper interconnects, a Chinese patent application CN102856249A disclosed a method which depositing a thin film after the Electrochemical Copper Plating process, and then processing a thermal reflow, to eliminate the differences in thickness of copper due to the different pattern densities on the copper plated wafer. However, this approach has two drawbacks:
1) The high temperature of the thermal reflow will make low k dielectric material unstable, which will reduce the copper interconnect devices performance of sub-40 nm technology node;
2) The introduction of new materials in the copper interconnects brings risk to the stability of the process.
Additionally, another Chinese patent application CN102222638A disclosed a method including: depositing silicide after polishing the copper to be flush with the dielectric layer in the first step; next, performing a second polishing to solve the problem of copper residues. However, in this method, under the condition of high temperature and oxygen gas, the exposed copper on the surface is easy to be oxidized, which increases the resistivity of copper interconnects and decreases the performance of the device.
In summary, the prior art does not provide a method of forming copper interconnects, which could effectively eliminate the surface defects caused by the pattern densities in the processes of copper plating and/or copper polishing, such as erosions, polishing residues, and improve the effective thickness of the copper and device performance.